GECI's Roadmap Transitions to Lead-free Electronics
December 31, 1969 |Estimated reading time: 6 minutes
Compiled By SMT Staff
SCOTTSDALE, Ariz. - The Global Environmental Coordination Institute (GECI) formed a six-step roadmap to act as a timeline for the electronics industry to develop lead-free PCB technology, eventually leading to product introductions using lead-free solders.
The first two steps, the definition of the Pb-free process and the solder material system choice (Sn/Ag/Cu), are completed, according to a GECI press release. A Printed Circuit Board Assembly Process Guideline is targeted for completion in Q402. GECI expects leading electronics manufacturing services (EMS) providers to begin qualifying the assembly process in 2002 and 2003, and product qualifications should take place from 2002 onwards. The final step, Pb-free conversion for every market application, will be tracked by GECI.
GECI, a network of organizations, began in Q400. Its nine initial consortium members, which represent their member companies, are High Density Packaging User Group (HDPUG), IPC - Association Connecting Electronics Industries, the JEDEC Standards and Technology Association, the Microelectronics Packaging & Test Engineering Council (MEPTEC), The National Electronics Manufacturing Initiative (NEMI), the Semiconductor Assembly Council (SAC), Semiconductor Equipment and Materials International (SEMI), SOLDERTEC (ITRI UK), and the Industry Technology Research Institute (ITRI Taiwan). HDPUG currently is managing GECI's activities.
"Unless we have a roadmap, we cannot provide guidance to the supply chain, which is board assemblers or component suppliers, as to when they need to be ready for what kind of product line," said Vivek Gupta of Intel Corp., GECI roadmap task force leader. "That is the main reason we said we needed to provide guidance on what the timing needs to be."
Universal Opens Technology Center
BINGHAMTON, N.Y. - Universal Instruments Corp. is increasing its commitment to China with a new research and training technology center in Suzhou, Jiangsu Province, China.
The new 6,000 sq. ft. Technology Excellence Center is a world-class laboratory and applications engineering facility that will provide hands-on process and manufacturing training support for existing and potential customers in China. Additionally, the Technology Center will be used to demonstrate Universal's process and productivity solutions, as well as the company's production and semiconductor assembly equipment solutions.
Book-to-Bill Makes the Climb
NORTHBROOK, Ill. - The IPC PCB book-to-bill ratio for May was 0.96, meaning $96 worth of orders for new boards were received for every $100 billed (shipped). The ratio increased from the April level of 0.94. Sales billed (shipments) in May 2002 decreased 27.7 percent from May 2001, and orders booked decreased 14.1 percent from May 2001. Compared to 2001, PCB bookings are down 25.0 percent YTD, while PCB shipments are down 35.9 percent YTD.
May's book-to-bill level increased from April's numbers, and orders booked for May 2002 decreased 14.1 percent beneath the level in May 2001.
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Q & A: qualifying an assembly process technologyQualcon Appoints IPC Certification Trainer
ATLANTA - Qualcon appointed Teresita T. Grefal as IPC trainer. Grefal brings 12 successful years of teaching experience to Qualcon, including two years at Solectron, where she served in capacities including line leader/solder trainer, solderer and assembly operator. She holds a bachelor's degree from Montclair State University, where she graduated magna cum laude, and an associate's degree in elementary education from St. Mary's College, Philippines. Grefal is an IPC-A-610 certified Class A instructor, and also holds certification from IPC as a registered instructor for J-STD-001.
Syncron Launches as Design Environment Service Provider
SCOTTSDALE, Ariz. - Syncron Technologies has launched as a design environment service provider (DESP) focused on process innovation and technology services that reportedly enables high-speed electronics designers to shorten product development time and reduce costs.
This peer-to-peer design environment is said to integrate multiple suppliers, engineering disciplines and design systems through proprietary software applications, state-of-the-art Internet technology, and professional services it provides as an integral part of the process.
The DESP is said to offer the first secure, open and flexible design environment, which transforms fragmented design environments into a design-to-manufacturing process that decreases design iterations, eliminates process interoperability issues and maintains corporate parts libraries.
Q:What steps should be taken to qualify a new assembly process technology in my manufacturing facility?
A:The qualification steps for high-volume production of new assembly technologies required for 0201 passive components, fine-pitch CSPs and flip chip devices will differ depending on the manufacturing operation's existing capability, experiences and internal requirements. The following case describes a typical process qualification methodology that was performed by SiemensDematic for an EMS provider who was implementing an 0201 assembly process into their standard SMT manufacturing line.
Phase 1: Metrology Equipment Gage Repeatability and Reproducibility (GR&R). GR&R tests were performed on solder paste measurement and component placement measurement tools to isolate disruptive factors. GR&R for the measuring equipment was performed with adequate measurement points over multiple trials. Acceptable results were recorded for both equipment sets, ensuring that the tools measured solder paste volume/height and component placement accuracy.
Phase 2: Process Capability (Cpk). Cpk was determined for the printing and placement processes using a replicate count of 192 for each operation. Different pad configurations determined the effects of multiple stencil opening sizes and thicknesses. The Cpk of the X/Y offset for component placement was performed using multiple equipment sets and test boards with various placement orientations. Initial placement tests were run using double-sided tape to isolate the placement process from the solder paste effects. Then the full Cpk study using solder paste was performed, taking all possible influencing factors into consideration.
Phase 3: Process Qualification. A DPM run demonstrated the process required for high-yield, high-volume 0201 placement. The run simulated actual production conditions and three boards were built to validate process setup using five different pad configurations. Following setup confirmation, approxi-mately 100 boards were built and the pickup reliability of the 0201 components and the defect level of the completed boards were monitored. More than 225,000 components were picked for this part of the qualification phase. Overall 0201 component pickup reliability using three different placement machines was determined to be over 99.9 percent. The DPM placement run also identified the main defects, which in this case were present for one pad design configuration. This phase quantitatively proved recommended pad size and configuration.
Craig Beddingfield is senior marketing manager, Advanced Assembly Technology for SiemensDematic Electronic Assembly Systems Inc., Norcross, GA.
SMTA International Features Workshops
MINNEAPOLIS - Two half-day workshops on September 26 at the Donald Stephens Convention Center, Rosemont, Ill., will be of interest to industry professionals.
"Creating Reflow Soldering Profiles For Convection-dominant Ovens" will be led by Conference Chair and SMT Magazine Advisory Board Member Rob Rowland, RadiSys Corp., from 8:30 a.m. to 12 p.m. This workshop will review and discuss topics associated with reflow soldering using convection-dominant ovens including time/temperature profiles, oven settings, conveyor speed calculation, profiling methods and profiling equipment. Related material topics will be covered as well. Information about oven heaters and conveyor configurations also will be presented.
"Flex Circuits & Flex-based Packages" will be led by SMTA Vice President of Technical Programs Ken Gilleo, Ph.D., Cookson Electronics, also from 8:30 a.m. to 12 p.m. This workshop will highlight the key dissimilarities between flex materials and processes and those of traditional rigid PCBs. The basics of flex materials, processes, constructions and assembly will be summarized, and the popular new flex-based packages that include wire-bonded bare die-on-flex will be covered. The focus will be on why flex was the first and best chip carrier for solving cost and high-density problems.