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CSPs:Paving the Way to Electronic Hardware Miniaturization
December 31, 1969 |Estimated reading time: 10 minutes
What's new with chip scale packages (CSP)? Quite a bit actually, if you follow reports and technical papers from the Surface MountCouncil (SMC), the National Electronics Manufacturing Initiative (NEMI) and APEX 2001.
By David W. Bergman
The continued emphasis on faster, smaller, lighter and lower cost electronics systems is making component, board and system packaging more complex each year. The portable products shown in Figure 1 continue to drive the component package area. The increase in complexity is due to wider use of fine-pitch, thin array surface mount packages the key to electronics products miniaturization. Though finer-pitch (0.80, 0.65, 0.50 and 0.40 mm) array styled packages are increasing, most components on the typical motherboard of a desktop computer remain at 1.27 and 1.00 mm pitch. Portable systems are moving to the finer-pitches and thinner profiles at much faster rates.Figure 1. Portable products continue to drive electronic components to be denser and more complex.
Figure 2. Package forecast by lead count range.
Based on industry predictions, one would believe that all component packages have more than 200 input/outputs (I/O) and that number is rising. Actually, components with the highest usage have counts from 4 to 68 I/Os (Figure 2). Over 80 percent of all components fall into this category, while less than 5 percent have more than 208 I/Os. This number may determine the crossover point between peripheral leaded component style packages and array type formats. The conventional leaded packages cannot be ignored, as can be seen by Figure 3. They will remain the majority of the volume, even until 2004. Many peripherally leaded, lower I/O count devices, such as memory and logic devices, are converting to area-array packaging formats as either ball grid arrays (BGA) or fine-pitch BGAs (FBGA).
Figure 3. Forecast of conventional leaded packages.
FBGAs/CSPs provide a potential solution where low weight and small size are requirements. These packages are only slightly larger than the chip itself, and are available in various configurations and material combinations. Figure 4 shows two solutions, with respect to package size, array I/O pitch and number of rows for the maximum possible pin count, for depopulated area-array FBGAs/CSPs. For these packages, the solder ball pitch is a fraction of that of the pin through-hole (PTH) on the substrate. Fan-out wiring connections are required on the substrate to reach the PTH. To minimize the fan-out requirements, only a few of the outer rows of the area-array connections are used. FBGAs/CSPs at 0.5 mm pitch will put pressure on the substrate interconnect density for I/O escape to reach the interlevel vias or the substrate's PTH. These packages primarily are used today in low pin count applications. There they provide potential advantages of higher performance, higher density and chip shrink transparency. For applications in which FBGAs/CSPs are redesigned to the minimum size possible each time the chip size is reduced, a corresponding redesign of the substrate onto which the packages are assembled will occur.
To accommodate BGA packages in 2001 for the high-performance market segment, the substrate should have 0.80 mm pitch PTHs, with a sufficient number of signal layers to access 14 outer rows underneath the BGA substrate. To accommodate FBGA/CSP solutions in 2001, the metal wiring on the top layer of the substrate must access the three outer rows. This means that the substrate should be capable of placing two signal lines between the two adjacent pads at 0.4 mm pitch as indicated in Table 1. Alternatively, build-up layers may be used to access the third and higher rows should pad pitch reduce.
Figure 4. CSPs and TFBGAs provide a potential solution where low weight and small size are requirements.
Real Estate DriversThe real estate constraint has contributed to the widespread use of surface mount devices (SMD), which are not only smaller, but also enable component mounting on both sides of the board. As pin counts increase, however (even with surface mount), the conductor-to-conductor pitch must decrease to keep the package size within a practical range for manufacturing. For example, when the pin count increases beyond 84 pins, decreasing pitch from 1.27 or 1.00 mm to 0.80 or 0.50 mm allows higher pin-count packages without a corresponding package size increase. There is an unwritten rule about real estate constraint for surface mount packages: the package size must be around 40 mm (1.50") maximum per side. The FBGAs and other CSPs are topping out at 21 mm (0.83"). This is largely because most pick-and-place machines have a field of view limited to about 40 mm maximum (although there are a limited number of models that can handle larger packages).
As the peripheral leaded package pin count increases above 200, the corresponding package sizes are approaching the 40 mm per side maximum that creates a plastic package overmolding warpage problem. This translates into a harder time maintaining the tight 1.0 mm (0.004") maximum coplanarity allowed. Plastic packages above 40 x 40 mm are not practical if the coplanarity is 1.0 mm.
As the package body size increases on peripherally finer-pitch packages (0.50 and 0.40 mm), the lead skew (bend) and coplanarity become equally critical issues. This is why the popularity of 0.40 mm pitch packages has not risen in the last few years. Pitches below 0.40 mm have been abandoned except in unique custom applications.
Market Drivers for CSPThe array CSP definition rapidly has developed over the past few years. The first definition was any package less than 1.2 times larger than the die size generically was called a CSP, and the number of different variations could be counted on one hand. Today, with more than 70 different variations of CSPs available and more being developed monthly, it has been difficult for the immediate customers and end users to keep track of what is being developed and how to classify variations. The end customer's requirement to get a new high-technology package at the older leaded technology's cost (or less) drives new family variations to be developed. Many new CSPs carry an extra cost penalty known as a royalty fee to cover the intellectual property (patents, trademarks and copyrights) for CSP family designs, construction, processes and materials. The different variations are developed to meet the customer's requirements, while keeping the cost as low as possible. The old days, when a single package design, construction, process and material were standard, have been supplanted with new variations.
The basic definition has been replaced with two standard definitions meant to further refine the original, while not limiting the ability of the CSP developer to use different designs, processes or materials.
A die-size BGA (DSBGA) or die-size land grid array (DSLGA) is a type of BGA or land grid array (LGA) package in which the body size coincides as closely as possible to a specific die size. This package is sometimes called a "real chip size" BGA, LGA or CSP. Package body dimensions accommodate die assembly with a specific size only, and these body dimensions will change as a result of future die size changes. The package outline may be square or rectangular, but this aspect ratio also may change as a given package is redesigned to conform to a new die size. The aspect ratio likely will differ for devices of the same functionality from multiple suppliers. The controlling factor for the DSBGA or DSLGA package standardization is the size and aspect ration of the ball or land array.
A "flange-type" ball or LGA package is a type of BGA or LGA package whose body size (length D and width E) is defined without regard to a specific die size. The body dimensions accommodate die assembly with various sizes, and usually will not change as a result of future die shrinks for a specific device function. The package is called a flange-type because the substrate or carrier typically extends outward beyond the perimeter of the die, forming a flange with respect to the die. Some type of encapsulant or lid usually covers the extended portion of the substrate.
These definitions exist in the JEDEC (JC-11) Committee's 95-1 Design Guides and are used to determine which mechanical package outline families are standardized. This standardization fixes mechanical dimensions of length, width, thickness, pitch of the array, ball or land size, and the array depopulation if present. With the present CSP development activity, design, construction, process and material standardization do not seem likely. What will cause a reduction in CSP variations is the lowest cost solution for the customer's needs. As the CSP market develops further, the highest cost variations will be discontinued.
And as microprocessor performance and speed increase, pin counts will, too. This trend will continue despite the fact that using multilayer packages with in-package capacitance for decoupling will enhance these packages electrically. For cost reduction, thermally and electrically enhanced packages will become common, however, the reliability concerns in such packages first must be addressed by the industry. Board assembly complexity will increase because packages of varying lead pitches, including PTH will be used. To reduce board complexity and increase manufacturing yield, BGA packages will become common because they reduce process complexity for the user. And despite complexity in packaging and assembly, the primary driver will continue to be cost.
Thin Fine-pitch BGA (TFBGA) TFBGA consists of a bare, peripherally leaded integrated circuit (IC) die that is either connected using single layer TCP tape automated bonding (TAB) to the top of a double-sided flex circuit or a multilayer laminate. FBGA options continue growing with the formation of new ideas. Over the next couple years, the most cost-effective options will become the clear-cut winners.
System in a Package (SiP)As OEMs continue to push the envelope with portable and automotive electronics, leading to the need for multiple functions per package, SiP will be on the verge of explosion. The demand to apply multiple functions in one package is being driven by the portable and automotive market places. SiPs are packages with multichip or few chip packages with passives included in the over-molded package configurations (Figure 5). Figure 5. SiPs are packages with multichip or few chip packages with passives included in the over-molded package configurations.
Reworkable Underfill Materials As area-array packages such as CSPs and flip chips replace leaded SMDs, new challenges to reliability continue to arise. Solder joint stresses due to coefficient of thermal expansion (CTE) mismatch of flip chip and laminate carrier's generally are relieved by underfilling the interspace between the chip and the carrier. The presence of the underfill ameliorates the problems caused by mismatch in the CTE of the board, solder and package during thermal excursions. The mechanism of improvement is the redistribution of stresses throughout the load-bearing underfill material. Underfilling area-array, fine-pitch packages are becoming increasingly popular in board assembly for improving reliability under thermal and mechanical loading. It has been shown that for some packages, depending on the design and construction, underfill (filled systems) between the CSP and carrier can enhance the thermal cycling reliability by at least an order of magnitude. SMD reworkability in high-volume production always has been taken for granted. However, introducing underfilled area-array components raises new issues regarding their reworkability because most current underfill materials are polymeric nonreworkable thermoset materials. The drawback of traditional underfills is that the electronics assembly cannot be reworked once the polymer is cured. As CSPs increase their prominence in mainstream use, the industry will need to find a process that allows rework.
The study concluded reworkable materials performed on par with or better than the nonreworkable control assemblies prior to rework in terms of thermal shock. The rework process was efficient and did not require additional time compared to the standard rework process. Standard rework equipment can be used; cleaning and replacement processes need to be better defined. Underfilling the assemblies significantly improved CSP mechanical shock (drop test) performance. The rework process used did not degrade the thermal shock reliability of adjacent CSPs. Additional work is required to optimize and characterize the effect of rework; more work is being planned.
ACKNOWLEDGEMENTThanks to the SMC and specifically to Mark Bird of Amkor; to NEMI and to Nael Hannan and Puligandla Viswanadham of Nokia Mobile Phones.
DAVID W. BERGMAN, vice president standards, technology and international relations, may be contacted at IPC Association Connecting Electronics Industries, 2215 Sanders Rd., Northbrook, IL 60062; (847) 790-5340; E-mail: davidbergman@ipc.org; Web site: www.ipc.org.