Implementing CSP Technology: A Controlled Approach to NPI
December 31, 1969 |Estimated reading time: 11 minutes
The contract manufacturer is now viewed more favorably by the OEM for its ability to respond quickly to packaging challenges and especially when the implementation of new assembly technologies, such as those with CSPs, are involved.
Cameron E. Presley
To successfully implement a new packaging technology such as chip scale packages (CSP), it is necessary to identify design boundary conditions, characterize process performance and implement process-control mechanisms. The goal is to recognize the challenges and sources of variation. Processes such as SMT tooling design, solder paste deposition, automated component placement and reflow soldering are the key characteristics. Those presented here apply to the new product introduction (NPI) of a Type II PCMCIA assembly employing CSP technology for flash-memory applications.
The Test Vehicle
A test vehicle was designed to investigate various assembly and material-handling concerns for implementing CSP technology into production and to anticipate customer requirements. Basic construction of the vehicle is representative of expected product classes that use CSPs (e.g., low-cost substrates such as FR-4). Because of the relatively small package attachment sites or pads, a planar finish is the most suitable.
For a more robust assembly process, three basic surface finishes are considered: immersion gold (Au), immersion white tin* and an organic solderability preservative** (OSP). Although solder-coated boards have been used with limited success for CSPs, the normal variation in solder thickness resulting from the hot-air solder leveling (HASL) process is significant relative to CSP feature dimensions.
Two printed circuit board (PCB) vendors are selected to fabricate the test vehicle. All attachment sites are non-soldermask-, or metal-, defined.1 Figure 1 and Table 1 detail test-vehicle construction. Advantages of using a test vehicle are:
- It represents a neutral entity that permits the manipulation of key variables, such as surface finish, substrate construction and supplier, whereas attempting to investigate variables is not readily possible with a completed electrical design. When seeking to characterize the quality of board-level interconnections, a daisy-chain continuity pattern is desired because the test die are relatively inexpensive and readily available for evaluation.
- A two-layer test vehicle with minimal plated through-holes (PTH) is more cost-effective. In fact, with a neutral board design, many vendors will sample test vehicles to participate in qualification tests they feel will yield potential production-quantity business.
- Because of design change and economic latitude, multiple designed experiments can be performed quickly and inexpensively, leaving more time for process development. The potential for success during the knowledge transfer to production processes increases. In this case, the knowledge gained was transferred directly to prototype, pre-production and production units of a Type II PCMCIA card with CSPs. This article describes highlights of one of the design of experiments (DOE).
Experimental Approach and Results
CSP under assembly-process development. A µBGA is selected to develop the CSP assembly process. The CSP planned for production use is geometrically similar to the µBGA with these exceptions: internal die-to-package interconnection, interposer substrate material and two additional solder spheres or I/Os. Table 2 details the different CSP physical dimensions. CSPs are considered moisture- and electrostatic-discharge-sensitive devices and are handled in accordance with industry governing standards.2,3
Test-vehicle procurement and incoming inspection. Test vehicles from two vendors with comparable PCB fabrication capabilities are sampled; boards are received and measured for dimensional integrity. In addition to visual inspection of critical board dimensions, the boards with immersion-gold-surface finishes are measured for gold and barrier-metal (nickel) thickness using an X-ray fluorescence (XRF) machine. The test vehicles are shown to be in specification with the desired thickness of immersion gold and nickel. For organic solderability preservative (OSP) surface finishes, it is nearly impossible for the contract provider to perform incoming quality control measurements of coverage or thickness uniformity. This is because OSPs are organic compounds that cannot be readily measured using mainstream PCB inspection tools such as XRF. The immersion-white-tin coating is measured via cross section and sequential electro-chemical reduction analysis (SERA) by a third party laboratory. All substrates are in conformance.
Solder paste deposition and stencil design. A DOE approach is chosen to determine optimal solder paste deposition process settings and stencil design. It is performed to optimize stencil printer settings such as squeegee speed and pressure, snap-off, and snap-off delay.4 A second DOE is performed to help resolve key stencil-design features such as aperture dimensions, shape, stencil thickness and solder paste (i.e., water-soluble vs. no-clean). For simplicity of analysis and sensitivity to process response, a 4 Factor - 2 Level Full-factorial (24) design is performed (Table 3).
The only factors studied for the latter analysis are stencil thickness, aperture size and shape, and solder paste under the combinations shown in Table 4.5,6 Five boards for each factorial combination and a total of 20 solder paste height measurements per board were taken using a tabletop laser-scanning microscope. In parallel with measuring solder paste heights, the cross-sectional paste deposition area, or pad coverage, was determined by the 2-D post-print inspection camera and software. By characterizing the solder paste height in conjunction with the 2-D paste coverage, the representative paste volume deposited can be calculated.
Figure 2 illustrates the results of the full-factorial designed experiment. The response is subdivided and scored based on the target solder paste height and the deviation from the target, as well as absolute value of the solder paste coverage. A scoring system with a maximum score of 10 and a minimum of one is selected (Table 4).
A linear model for scoring is used; graduation within the scoring system is based on observed experimental variance. The cumulative or print-performance score is the sum of the solder paste deviation and coverage scores. For reference, the target solder paste height for each condition is the stencil thickness plus 0.0005".
Analysis of the factorial table reveals that the two most important factors within the stencil design are aperture size and stencil thickness. This is intuitively based on common experiences of the effects of the stencil aspect ratio on paste release. In this instance, the best paste release, print definition and solder paste volume is observed using a 0.005" thick stencil, a 0.014" square aperture and no-clean paste. The corresponding aspect ratio is 2.8 and the area ratio is 0.7, which are values greater than the desired minimums of 1.5 and 0.66, respectively. The differential response for aperture shape and solder paste chemistry are within the margin of experimental uncertainty.
The enhanced release of the no-clean paste apparently is because of its resistance to humidity changes. As the work environment becomes less humid, aqueous-based chemistries tend to dry out. No-clean flux vehicles are not as susceptible because they do not rely on organic acids for flux activation. As for the effects of aperture shape, by using a round opening, the area ratio is unfavorable at 0.54 vs. 0.7 using a square aperture. Interaction effects support the main effects and stencil design parameter selection.
Component placement. All CSPs assembled onto test vehicles are received from the supplier in waffle trays. Components are placed onto a glass plate using a flexible placement platform. After tweaking component placement to the desired accuracy level using the test vehicle, the glass plate is introduced to quantify the level of machine placement accuracy and repeatability. The glass plate is designed so that bumps on the µBGA correspond to electroplated targets on the glass-plate surface.7 The latter is coated with "tacky" tape to provide a temporary adhesion with the CSP. After placement, the glass plate is inverted and viewed under a high-magnification scope to inspect for CSP bump-to-target registration. (The targets are positioned so that every other bump feature exactly matches the glass-plate target, a distance of 500 µm apart.)
After placing approximately 35 µBGAs, the corresponding positional accuracy is found to be within 60 µm, as represented by the equipment manufacturer. A process capability index (Cpk) of 2.0 is observed, indicating that after control is established, a stable process is possible under the process conditions investigated. Figures 3 and 4 illustrate glass-plate design and the method of calculating X/Y positional accuracy and repeatability.
Component placement was further characterized by placing µBGAs on the FR-4 test vehicle. Solder paste is screen printed on the vehicles before placement and transmission X-ray inspection verifies component alignment before transport to reflow.
Reflow soldering is performed using an eight-zone convection reflow oven. The oven`s heated length is 98" and an optional cooling zone is used within the reflow soldering analysis. The oven also is equipped with a closed-loop, static-pressure control to hold the convection rates in each zone (by monitoring the static air pressure, typically 1.0 to 1.2" H2O gauge) within the plenum box. Because of the relative low mass of the CSP devices vs. those of surrounding SMT components on production assemblies, air flow rates at the board level must be controlled to minimize part disturbance before soldering. The paste tackiness is solely relied upon to secure the part in place. Maintaining and controlling the mass flow rates of air at the board level proved to be an invaluable CSP assembly tool.
The profiles selected for assembly accommodate solder paste properties such as flux vehicle and alloy, CSP bump alloy, the most vulnerable component`s maximum temperature, dwell time at maximum temperature, and recommend ramp rates. Although the CSP was the most vulnerable component, a maximum temperature of 225°C is desired for process development. Another critical profile parameter sought is a ramp/decline temperature change rate of 3° to 4°C per second. To achieve adequate solder wetting and bump collapse, a time above liquidus (183°C) of 60 to 90 seconds is desired.8 Figure 5 depicts the primary reflow profile.
The time-temperature reflow profile is determined using a data logger system and an on-board thermocouple attachment. Thermocouples are attached to the desired location by drilling through the back of the board and soldering to the CSP solder bump using a high-temperature solder alloy (Sn5/Pb95). Additionally, a stress relief to the thermocouple wire is achieved at the point of attachment by applying a small amount of thermosetting adhesive.
To characterize the quality of reflow, X-ray inspection checks for voids within the solder joint, solder bridges or shorts, and poorly collapsed balls. To ensure reflow effectiveness, samples are prepared for destructive analysis and cross-sectional inspection of solder joint integrity. Figure 6 displays a solder bump after collapse. Note positive wetting to the sides of the attachment site, indicating that the solder bump reached an acceptable temperature to wet to the pad and form a mechanical and electrical connection. Under magnification, the interfacial bond area between the solder bump and the attachment site has a smooth and continuous intermetallic layer indicative of a proper metallurgical reaction between the solder and copper pad. The intermetallic layer indicates that the protective coating on the solder attachment site, whether inorganic in the case of immersion gold and tin or organic with the OSP, was not compromised and a solderable surface was present.
Finally, in addition to analyzing the solder bump-to-board interface, the bump-to-package interface is inspected to ensure that the assembly-level reflow process did not compromise the package-level connection.
Knowledge Transfer
After the assembly trial of the µBGA on the test vehicle, the parameters determined for substrate and SMT tooling design, component placement, reflow soldering, and inspection are transferred to the assembly of a Type II PCMCIA card using the production CSP. The latter package, intended for flash-memory applications, successfully met the small form-factor, lightweight, high-density assembly requirements. During prototype and pre-production phases of the NPI, the process parameters derived during development were verified and validated to yield a robust assembly process. The PCMCIA card had other devices that were suspected to require more solder than afforded by a 0.005" thick stencil. Similarly, one of the surrounding components possessed a termination plating that required slightly higher reflow profile temperatures.
In the end, only minimal process changes established during the development phase were required, and a quality product was produced and delivered on schedule within the expected cost.
* OMIKRON.
** ENTEK Cu 106A.
Tessera`s µBGA TV-46.
ACKNOWLEDGEMENTS
The author acknowledges the assistance of Data Circuit Systems Inc. and Viasystems Inc. for PCB samples and test-vehicle assembly. Thanks are also extended to Denis O`Connell of Alpha Metals, Technical Services Group, for performing cross-sections and supplying photos for archive and publication.
REFERENCES
1 Comprehensive Users` Guide for µBGA Packages, Intel Corp., 1997 and 1998, Figure 16, p. 26.
2 J-STD-033, January 1999, Official Representative Proposal, JEDEC, Arlington, Va.
3 IPC-CM-770, January 1996, Section 26.2 through 26.3, Rev. D., Lincolnwood, Ill., 1996.
4 Donald C. Burr, "Solder Paste Printing Guidelines for BGA and CSP Assembly," SMT, January 1999, p. 70-74.
5 M. Wang, K. Nakajima, et al., "Investigating Printing Process for CSP Assembling," Proceedings of SMTA International 1999.
6 Keki Bhote, World Class Quality, AMACOM, New York, 1991.
7 Glass substrate provided for machine acceptance criterion by Siemens Energy and Automation.
8 F.G. Yost, F.M. Hosking and D.R. Frear, The Mechanics of Solder Alloy Wetting and Spreading, Van Nostrand Reinhold, 1993.
CAMERON E. PRESLEY may be contacted at K*Tec Electronics Inc., 1111 Gillingham Lane, Sugar Land, TX 77478; (281) 243-7982; Fax: (281) 243-7882; E-mail: preslec@ktecelec.com.
Figure 1. Test-vehicle construction. All attachment lands are non-soldermask, or metal-, defined.
Figure 2. Full-factorial DOE results: Y-hat surface plot of print performance stencil thickness vs. aperture size constraints (a: aperture shape = 0; paste chemistry = 0) and aperture shape (b: aperture size = 0; paste chemistry = 0).
Figure 3. Glass-plate design for component placement evaluation.
Figure 4. Calculation method for determining positional accuracy and repeatability.
Figure 5. Reflow profile (time vs. temperature). To achieve solder wetting and bump collapse, a time above liquidus of 60 to 90 seconds is desired.
Figure 6. Solder bump-to-board interface after collapse. Note positive wetting to the attachment site, indicating an acceptable temperature to form a mechanical and electrical connection.