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By Tamara Seyer
Smaller components and boards have forced the creation of new test techniques.
The dawn of the information age has created both the desire and need for faster computing. The need for cellular phones, digital cameras, compact disc players, computers, printers and scanners has become so great that these items need to be used in any environment, forcing the manufacturers of these products to make them portable and more convenient. Society has demanded miniaturization and eliminated its tolerance of poor quality. No longer can a company release a product before it has been completely tested. Every printed circuit board (PCB) must be tested for utmost quality.
Testing these small PCBs has become a challenge because of the limited access available for probing various components. Not only are the boards themselves shrinking, but the devices on these boards are becoming extremely small, as well. Because of the size of these components, the ability to access them for testing is a significant problem.
Here is the overall challenge: The boards must be tested for quality; however, the components can no longer be electrically isolated for testing. If the devices cannot be tested individually, they may have the ability to be tested functionally. Failures at functional test are both time-consuming and costly to diagnose. If there is no functional test to account for these inaccessible devices, they may get tested by the end user the most costly test available. It could easily result in high warranty costs or the loss of good faith with the customer. A loss of good faith could eliminate the possibility of repeat business and positive word-of-mouth advertising.
Hewlett-Packard has developed a new technology that addresses these limited-access challenges. This technology is an in-circuit test (ICT) technique that automatically generates non-powered analog cluster tests for resistor-, capacitor- and inductor-type devices that already have limited access and cannot be tested using traditional ICT technology. These are the same circuits for which test developers spend time and money creating analog functional tests. This test technique can significantly increase the fault coverage of a limited-access board without adding additional test points.
The first formal use of this limited-access technology on an in-circuit tester was on a digital signal processing (DSP) board from Matshusta (MEI) in Japan. The board was an audio board used in a full digital editing system. Originally this board had full access. However, for purposes of testing this new technology, random test points were selected to reduce the access to 70 percent of the overall board. Using this limited access, the fault coverage increased from 86 percent using standard ICT techniques to 98 percent when the new test technique was included. That is an overall 13 percent increase in fault coverage.
MEI's board had almost 475 digital parts and more than 400 analog parts. There were approximately 630 nodes, of which 70 percent were accessible. Because of this inaccessibility, 100 devices were tested using the limited-access technology. Out of all the clusters, 33 percent of the tests generated for them passed automatically because of accurately describing the board to the tester's software, while the remaining tests were successfully debugged. Although the run time was a bit slower than standard ICT, it was significantly faster than a functional test. To test all of the clusters, it took 31 seconds, averaging approximately 1.5 seconds per cluster. If these cluster devices were tested in functional test, having accurate diagnostic information would be unlikely. With this limited-access test technique, the diagnostics for each cluster are automatically generated. Although the throughput is slower, it is faster than functional test, with the additional benefit of having diagnostic information in the event of a failure. MEI was able to significantly increase the fault coverage of a primarily digital board without increasing the accessibility to the board.
The concept of limited-access technology is based on the idea of a matrix. If the circuit definition is known and limited access exists, then a model based on the components in the cluster can be generated using voltages at the accessible nodes.
Figure 1 illustrates an analog circuit surrounded by active components. The first step of the limited-access test technique is to determine if clusters exist on the board, independent of probing locations. The technology is able to define groups of components that are electrically isolated by identifying all active components. Because of the electrical properties of active components, they can be considered to be open. The software automatically identifies this situation and removes these devices from consideration. Upon doing this, the circuit in Figure 2 remains.
In Figure 2, all active components have been omitted, leaving five resistors and three capacitors in the circuit. The system now traverses the circuit and uses the accessibility information of the nodes to separate it into clusters. For each cluster that the software identifies, a mathematical model that describes the set of "passing" voltages at all accessible nodes is constructed. These voltages correspond to the devices having all the possible values comprised within their allowed tolerance ranges. Figure 3a illustrates such a set of voltages at V1 and V2 of the example circuit. The graph in Figure 3a depicts the change in voltages to aid in visualizing the "passing" region around the origin.
Figure 3b is essentially the same graph. It shows the boundaries of the actual model if all possible points could be plotted. The limited-access test technique automatically finds the boundaries of this region. If a voltage measurement falls within this region, the technology will determine that the cluster circuit is passing. This region is therefore considered the "passing" region.
What if a voltage measurement does not fall within the predetermined passing region? How does the limited-access test technology diagnose a failure to single or multiple components?
If a single component is allowed to infinitely vary while all the remaining components in the cluster remain within their respective tolerance regions, the parallel boundaries in Figure 3b can be extended to represent each individual component (Figure 4).
Figure 4. The space between the parallel lines represents the voltage measurements associated with each individual component.
Figure 4 also describes how this new technology can diagnose various failures. Each point (A, B, C or D) represents a voltage measurement. Point A falls within the passing region; therefore, the circuit is diagnosed as good and moves on to the next test. Point B falls within the boundaries of R1 only. Therefore, the diagnosis indicts only R1. Another scenario occurs when multiple devices represent the space of a failing voltage. For example, point C falls within the region associated with R1 and C1. In this case, a failure cannot be differentiated between the two devices and both devices are indicted. The fourth failure possibility occurs when the voltage measurement falls outside all represented space. When this happens, the system cannot determine the failing components and indicts the entire cluster, meaning that all analog components in the cluster are suspect.
An analog cluster of a known good board will pass automatically if it is modeled accurately and the components and topology are correct. If the model cannot be corrected to match the true topology on the board, there is a "learn" feature that can be used to quickly allow the cluster to pass. This new feature allows the test engineer another avenue for those times when the model cannot be corrected. This feature forces the cluster to pass. It finds the boundaries within which the cluster will pass and automatically adjusts those boundaries to allow the cluster to pass.
While this new limited-access test technique may seem a bit complex, it is not magical. There is a definite method to using it and, if used properly, it can significantly increase fault coverage.
TAMARA SEYER is the magic test application engineer for Hewlett-Packard, Manufacturing Test Div., 815 SW 14th St., Mail Stop BU213, Loveland, CO 80537; (970) 679-5658; Fax: (970) 679-5112.