BGA/CSP Issues

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This month, experts in the area of ball grid array (BGA) and chip scale package (CSP) technology discuss current and future BGA and CSP issues. Topics addressed in this issue include challenges, trends and standardization of BGA and CSP technologies.

Q What do you think are the remaining challenges/obstacles facing the widespread adoption of BGAs/CSPs?

MacWILLIAMS: Challenges/obstacles include: achieving cost targets (i.e., cost parity with lead-frame type devices); North American infrastructure; cost-effective HDI substrates; coefficient of thermal expansion (CTE) compliance in large ball-count devices; and production sockets.

MARRS: We see that BGAs are already under widespread adoption. They are present in most every type of product shipped today, including PCs, workstations, phones, pagers, telecom, medical, industrial and automotive. For the market to grow, BGAs must compete with quad flat packs (QFP).

In many areas, BGAs are superior to QFPs, and this is why they have won market share. Generally, BGAs win for cost/performance and cost/size, as well as for flip chip interconnect situations. QFPs still dominate for purely cost purposes in 64 to 208 pin counts.

PITTAM: I think the remaining obstacle is surviving the industry's current economic cycle. There will be no widespread adoption if companies cannot survive this.

LIN: BGA cost is one of the major factors influencing the widespread adoption. This is impacted by the sole Bismaleimide Triazine (BT) supplier source with high substrate raw material cost. The remaining challenges that we face include warpage problems for lower profile packages with thin core material, and the emergence of fine-pitch requirements to push substrate suppliers with tighter design rules.

HAMANO: 1997 was the first year that first-generation CSPs moved into volume production. In the digital video, digital camera, mobile computer and cellular phone markets, it was inevitable that CSPs would be widely adopted. The major benefit in these markets is miniaturization and light-weight products. The PC market is a giant unexplored market for CSPs. In 2000, direct RDRAM could open up the high-end server market because of its excellent electrical performance.

Widespread adoption of sub-$1,000 PCs challenges manufacturers to achieve price parity. It is not enough to compare CSP cost with conventional thin small outline packages (TSOP) or QFPs the total system cost must be analyzed. A cost-effective, second-generation CSP will have widespread acceptance.

OLACHEA: First is the name confusion. We think the focus needs to be on "shrink" BGAs, with a ball pitch of less than 1.0 mm (in other words, CSP-BGA). Secondly, and this is a vice/virtue for the CSP-BGA, is the absence of a single industry-wide adopted standard for CSP-BGAs. "Custom" is the pivotal maxim for producing CSP-BGAs because of the end-product application demand (footprint, size and weight). Our industry still prefers to have standards and guidelines a defined "box."

Q What trends will we see in the manufacture and use of BGAs/CSPs this year?

MacWILLIAMS: Trends include: chip scale devices (e.g., μBGA and molded array packages); system-on-chip BGAs; multichip package (MCP) BGAs; 1 mm pitch; flip chip BGA; 1,000 I/O ASIC devices; the continued trend from CBGA to PBGA; increased usage of thermal BGA packages; increasing North American BGA manufacturing capability; and announcements in substrates.

MARRS: We see the following trends:

  • The transition to four-layer boards in standard BGAs.
  • The increasing use of multi-die PBGAs and integrated passives. Of real interest are the high density multi-die chip scale formats it's amazing how much we can pack into an 8 mm package. The wireless/portable telecom people really like these solutions.
  • Decreasing BGA pitch. Most PBGAs are 1.27 mm pitch. But many new designs are in 1 mm format.
  • Increasing chip size BGAs (which are just shrunken BGAs).
  • Increasing flip chip BGAs especially for very high pin counts (more than 600 balls).
  • Increasing demand for quicker time-to-market of more complex products.
  • Increasing need for finer featured PCBs.

PITTAM: For emerging trends in manufacturing and usage of BGAs, reliability and "survivability" play key roles. For manufacturing trends, there are two possibilities. One trend is to have capabilities within the company to assemble device-specific units. Thus, there is one assembly line for one type of device. This ensures the quality and reliability of the device. Another trend is to assemble units in the cheapest way possible one assembly line handles several types of devices. This cuts down on capital and start-up costs and also maintains "survivability."

LIN: The uses of BGAs this year will expand to include higher thermal performance, frequency, EMI management and lower/smaller profile package size application. Due to these application requirements, BGA manufacturers will be forced to develop fine-pitch BGA, thinner/smaller BGA substrates, multilayer substrates and thermal performance enhancement on substrate design.

HAMANO: A cost-effective CSP will debut this year in the form of a second-generation CSP. It will have cost parity with conventional TSOPs and QFPs. This creates a broader market for CSPs that includes the huge PC memory market.

The stacked MCP is a new trend. It accommodates two devices in a single package, e.g., SRAM on the top and flash memory on the bottom. It will be in large-volume production to supply the seemingly endless demand from the cellular phone market.

Another big trend at this time is the wafer-level CSP (WLCSP). These will be in production for specific customer applications. WLCSPs are a combination of bare die and a CSP. We call it "known-good encapsulated die" (KGED) replacing known-good die (KGD).

Q How do you see the BGA/CSP standardization issues being resolved and/or what steps need to be taken to develop well-defined BGA/CSP standards?

MacWILLIAMS: This is an issue for the Electronic Industries Alliance (EIA) and Joint Electronic Device Engineering Council (JEDEC). Market forces are helping.

PITTAM: I see the BGA standardization issues being resolved very slowly. There are just so many different packages and devices coming out from a variety of different companies. Everybody wants to emerge as the leader in their market niche. As leaders, they want everybody to follow their standards. Until well-tested, market-proven BGAs emerge in the forefront, there will not be a benchmark for standards available.

LIN: For normal and conventional PBGAs the standards are somewhat well-defined. To further develop the standardization of mini-BGA and build-up BGA, issues of layer structures and reliability need to be tackled.

HAMANO: Several standards and outlines/registrations have been published by JEDEC and the Electronic Industries Alliance of Japan (EIAJ). JEDEC published the MO-197 (USON; 0.50 mm pitch), MO-205 (LF-XBGA; 0.80 mm pitch), MO-207 (F-XBGA; 0.75/0.65/0.50 mm pitch), MO-210 (TFR-XBGA; 0.80 mm pitch) and MO-211 (F-XBGA; 0.50/0.40 mm pitch) outlines/registrations. EIAJ published the EDR-7316 (FBGA/FLGA) and EDR-7318 (P-VSON) design guidelines. EIAJ also published the ED-7311-5 (FBGA; 32/48-pin), ED-7311-6 (FBGA; 60/90-pin), ED-7311-7 (P-FBGA; 0.5 mm pitch) and ED-7311-8 (P-FBGA; 0.8 mm pitch) standards.

At this time, there are 56 CSPs in the world. It is very important to unify outlines, especially ball pitch, ball diameter and height, so a customer can use the same motherboard footprint and pick-and-place machine for all CSPs. Testing methods for second-level reliability has also been discussed by the EIAJ, as qualification criteria differ from customer to customer. As CSPs slim down to minimum packaging, they become more sensitive to reliability testing. It is critical to review test criteria and create industry standards. The discussion of real chip size package has begun, but we must study how to standardize the package or die size.

OLACHEA: "Chip scale" standards are a problem. The definition of chip scale changes when the die size is modified. The package size can vary as the die/chip shrinks or grows. Additionally, consumerization of end products spells custom IC package solutions. Installing standards limits the flexibility of creating chip scale, or other IC package, solutions. "Standards" as a paradigm are being challenged and replaced to enable rapid tooling and manufacture of packaging solutions for a very dynamic consumer market. My company has addressed this by providing flexible, well-defined CSP-BGA body sizes from 4 to 13 mm in 1 mm increments. This works well for customers who require a broader choice of IC package footprints for expanding product platforms. Additionally, it addresses the "standard" tray/socket footprint questions that arise when the semiconductor is subjected to test rigors.

Q What changes have you implemented to support and accommodate new and emerging BGA/CSP technologies?

MacWILLIAMS: Changes to support and accommodate new and emerging BGA technologies include: "X"GA socket technologies; RF microwave BGA device packaging; support for JEDEC standards activity; support for EIA ALCEM briefings that promote BGA packaging and interconnect product/technology initiatives; support for National Electronic Manufacturing Initiative (NEMI): Infrastructure, Roadmaps, Passive Integration; support for university research on array packaging and interconnect; support for a global OEM customer base with interconnect product development.

MARRS: We have a complete technical support team that provides help to customers and end users. Our Web site,, has information that is useful to designers and users alike.

PITTAM: One change we have implemented was to integrate the groups working on different BGA devices, enabling us to learn from each other's work and to plan in a productive manner.

We are also trying to ensure that equipment on all lines is easily convertible to handle different packages, devices, etc. Hardware, as well as software, is checked for future modification purposes.

LIN: As a professional BGA substrate supplier, Phoenix Precision Technology Corp. is not excluded in the new and emerging BGA technologies and businesses. We are contributing products and technologies to meet the BGA market trend. PPT technologies are available for multilayer products, thin core substrates, high thermally enhanced BGA substrates, alternative substrate material evaluation for cost reduction and developing processes such as build-up BGA products.

HAMANO: We have been proposing WLCSP as an emerging technology since February 1998. It is a real chip size package that allows a system designer to lay out a motherboard without wasting space. It also allows an assembly engineer to mount and replace chips on the motherboard with the same processes as for conventional CSPs, and allows a test engineer to test and burn-in much easier than a KGD.

We have also developed wafer-level testing (WLT) technology for functional and burn-in tests. Combining WLP and WLT will reduce cost because it reduces material, tool set, the assembly process, primary testing and the test socket.

We can use conventional front- and back-end equipment, which reduces new investment.

OLACHEA: My company has created a CSP-BGA program tailored to meet the customers' requirements and request for flexible solutions. We have recognized the limiting boundaries defined by lead-frame-based packages and have displaced them with user-friendly systems to enhance the success of advanced-product designs.

Q Are high-density substrates a limiting factor? Which substrate technology works for CSP?

HAMANO: From the perspective of economy, industrial use is still limited to a 0.8 mm pitch. From the package technology viewpoint, we can provide a CSP with 0.5 and even 0.4 mm pitch using tape or build-up substrate. From the substrate perspective, a state-of-the-art build-up substrate can be routed with the design rule of 25/25 μm in line and space, and 40/60 μm in via and land diameter, by using photolithography technology.

We have the technology to manufacture a high-density solution. The limiting factor is cost. A typical example is a memory module the industry cannot use build-up substrate for a memory module due to the big difference in cost compared to a conventional FR-4 subtractive PCB.

Test-socket and second-level reliability are other limitations. We can test some specific technology, like the membrane material, and we can guarantee second-level reliability of a CSP of less than 0.5 mm with underfilling resin from a technical viewpoint. But we must keep developing a price-parity solution.

OLACHEA: Yes and no. The design requirements, vendor, specified materials, metalization scheme(s), plating and other determining factors influence the degree of difficulty in sourcing high-density substrates. It is imperative to have clear and concise expectations communicated between customers and suppliers to achieve the highest degree of success. The substrate technology enjoying the greatest level of use today can be characterized as: soldermask defined, rigid laminate; two-metal layer construction; copper traces/conductors; BT polyimide; and laser-drilled vias.

John MacWilliamsSpecialist in Product Planning and Technology TransferAMP Technology GroupWilmington, Del.

Bob MarrsPresident & ChairmanAbpac Inc.Phoenix, Ariz.

Jason PittamPackage Development Engineering Team MemberMicron Semiconductors Asia Pte. Ltd.Flash Memory Package DevelopmentSingapore

L. Z. LinR/D Department ManagerPhoenix Precision Technology (PPT) Corp.Hsinchu City, Taiwan

Toshio HamanoDirector, APT MarketingFujitsu Microelectronics Inc.San Jose, Calif.

Gil OlacheaVice President, Marketing & New Business DevelopmentAbpac Inc.Phoenix, Ariz.



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