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The objectives of these studies are to develop optimized assembly processes, demonstrate the production assembly processes developed and provide reliable solder connections.
By Kazu Nakajima, Alington Lewis, Sammy Yi and Nicholas Brathwaite
There is no doubt that chip scale package (CSP) infrastructure is maturing. The electronics assembly market estimates that 500 million CSPs will be produced this year, doubling the number of units produced last year.1 The increasing demand for CSPs is currently breaking into the DRAM field. This expanding market and the trend towards miniaturization in portable, hand-held and personal digital assistant (PDA) cellular phones, digital cameras, camcorders and palm-type personal computers (PC) are driving CSP applications.2
From the beginning of on-board ball grid array (BGA) implementation, characterizing and optimizing the CSP on-board assembly process has been an ongoing project.3,4 Thermal shock, temperature cycling, high-temperature storage and humidity/temperature tests have been performed. Other major objectives of the project are to develop design- and process-control guidelines, and to integrate the process guidelines into production lines.
Based on past experience, a second test vehicle was designed for newer CSPs in a PC card format. The new test vehicle was populated with eighteen types of CSPs from twelve different suppliers, along with SMT components including small discrete devices (e.g., 0201 and 0402 on both the top- and bottomside). Process qualification and challenges will be described for this new test vehicle.
MethodologyThe process characterization and implementation development team included representatives from the company's design, process-development, prototype and manufacturing engineering. The implementation of the CSP on-board assembly process consisted of five phases:
- Process characterization
- Preliminary production evaluation
- Process test run
- Production-process confirmation run
The process-characterization phase consisted of two steps: initial evaluation and process characterization. The initial evaluation was performed to study the processes and determine which parameters were key variables. In process characterization, the primary processes studied and characterized were solder printing, pick-and-place, and reflow.
In the preliminary production-evaluation phase, the basic two-step process transferred from the prototype operation was evaluated for a production environment. First, the production process parameters were optimized based on the results of the preliminary evaluation. Second, the optical inspection, electrical tests and process-capability studies were used to optimize the process parameters of the next phase.
A test run was performed, with optimized process parameters, prior to the confirmation run. The objective of the test run was to verify the process on the production line, which was prepared to produce qualification test vehicles.
Phase four, the production-process confirmation run, was performed with optimized and pretested parameter settings. This phase was done to ensure that process performance was consistent and could reliably assemble CSPs on a board in a production environment.
The qualification phase involved sending the assembled boards to independent labs for reliability testing during the confirmation phase. The defined reliability tests exceeded most customers' expectations and, in some cases, were significantly more aggressive than tests previously performed.
Process-implementation VehiclesThe test boards were designed for Type II PC card dimensions of 5 mm exterior thickness and a maximum 4.5 mm interior thickness, with a PC card size of 54 mm width x 85.6 mm length. To fit into the card format, the test boards' actual dimensions were 72 x 48 mm and 0.5 mm thick. This included connector-footprint areas at both narrow ends and some holes and cutouts necessary for card assembly. The main connector was a PC card-standard 68-pin connector. A second I/O 25-pin connector was also used.
The first test vehicle used industry-standard designs, 0.004/0.004" line and space rules and 0.008/0.0015" drilling/land spaces for minimum via size, on double-sided FR-4 boards. The second test vehicle used a slightly advanced design, 0.003/0.003" line and space rules and 0.008/0.0012" drilling/land sizes as the minimum, on four-layer FR-4 boards. In accordance with previous studies on several types of BGAs, nonsoldermask-defined (NSMD) pad designs were applied for second-level reliabilities. The pad size was designed primarily to be the same size of the corresponding pad on the CSP (1:1 pad design) with some exceptions. For a metal finish of the first test vehicle, soft Au (0.5 μm thick) and Ni (5 μm thick) were employed as a wire-bondable and solderable surface finish. A flush Au surface finish was applied for the second test vehicle because there was no chip-on-board (COB) on it.
The PC card test vehicles required on-board assembly processes for both sides. For the first test vehicle, the topside was populated with CSPs, COBs and some small SMT devices. The bottomside was populated with peripheral leaded components, quad flat packs (QFP) and thin small-outline packages (TSOP). The second test vehicle had CSPs on both sides with some peripheral leaded components and some small SMT devices, of which chip resistors (0201) were the smallest size.
Several types of CSPs were selected for qualification based on the availability of test samples with daisy chains. Table 1 lists the selected types for the first test vehicle, while Table 2 lists the CSPs for the second test vehicle.
On the first test vehicle, two types of flex interposers were selected. One was a CSP type A with 46 and 188 I/O. Another flex interposer CSP, type B with 48 I/O, was chosen as an example of a molded flex interposer. A rigid ceramic interposer CSP, type C, was procured in a 324 I/O format with a daisy chain structure. CSP type D with 144 I/O was selected as a wafer-level assembled CSP. A total of seven CSPs in four types from four different manufacturers were assembled on each board. On the other hand, the newly designed second test vehicle was populated with 18 CSPs from 12 manufacturers in 14 different types. Types A through C were the same as those used on the first test vehicle, though Type C was improved in its pad design.
While studying the first test vehicle, the 188 I/O CSP type A and the 144 I/O CSP type D became unavailable from the manufacturers. The process characterization and implementation of the first vehicle were performed with two CSP type A 46 I/O, two CSP type B 48 I/O and one CSP type C 324 I/O.
The 188 I/O CSP was employed for the second test vehicle when it became available. All solder joints were electrically testable with daisy chains. All CSP joints could be tested at test pads designed around the components or on the bottomside of the board. Photographs of the first CSPs on a PC card process qualification vehicle, including the two missing CSPs, are shown in Figure 1.
Figure 1. The first test vehicle for CSP on-board assembly process implementation.
Assembly Process ImplementationThe first challenge was the solder paste printing process. In a recent case study, the solder paste printing process contributed to more than 50 percent of the defects in the entire SMT process.5 Area array and small size pads of CSP created another level of complexity. To ensure reliable CSP attachments, solder paste heights and volumes had to be controlled. The collapsible solder bumps used on several types of CSPs were designed similar to BGAs to provide the necessary volume for reliable attachments. Others with no collapsible solder bumps were more sensitive to the solder volume printed.
Both pastes* that were used were no-clean eutectic Pb/Sn solders with a powder type 4 (particle size: 25 to 38 μm, mesh size: -400/+500). These pastes use a modified rosin paste with improved activity to enhance wetting. The pastes demonstrate fine-pitch printing capability and accurate depositions, with rapid printing and excellent wetting properties.
Figure 2. Aperture surface before and after the electropolishing.
The stencil, a critical tool used for these studies, was laser-cut and electrically polished. One key reason for selecting the laser-cut stencil was the need for tapered and trapezoidal shapes with larger openings on the bottomside of the stencil. These apertures, with approximately 5° tapered openings, have proven to release solder paste well for such fine printing. In addition, the electro-polishing removed small burrs from the aperture's inner wall, improved the surface and ensured uniform release of the solder paste, thereby creating less smearing. Figure 2 shows a typical aperture-opening surface of a laser-cut stencil before and after the electro-polishing. For the first implementation, stencil apertures were designed primarily to be the same size as the pads, though some were modified as shown in Table 3. The modified square-shaped apertures also improved the paste volume control, especially for very fine openings.
The results of the studies on the first test vehicle for printing process capability:
Preliminary production evaluation
- Number of measurements: 280
- Average paste height: 0.006"
- Standard deviation: 0.0002"
- Process capability index (Cpk): 1.5
Production test run
- Number of measurements: 56
- Average paste height: 0.0061"
- Standard deviation: 0.0002"
- Process capability index (Cpk): 1.6
Both printer equipment types** had adequate alignment accuracy and printing consistency with the correct stencil.
The production line placement system was equipped with a bottomside vision alignment system for very accurate placement and a capable accurate placement of ±0.025 mm or less.
Since the CSPs' solder joints were not exposed to the oven environment, thermocouples on a profile board were located in joints underneath the CSP components. Six thermocouples were used on the profile board, which was the same board structure used for the test vehicle. Three of the thermocouples were located in solder joints underneath the CSP components, while the other three were located on the board surface and the lead of the surface mount devices. The cross-sections of CSP solder joints after the reflow are shown in Figure 3.
Figure 3. Cross-sections of the solder joints after reflow.
Reliability TestsThe primary focus for failure was joint fatigue of CSPs attached to a printed circuit board (PCB). The key factors that affected the reliability of CSP joints included temperature and coefficient of thermal expansion (CTE) differences between the component and the PCB. To evaluate the reliability of our CSP assembly processes, the process implementation vehicle was subjected to the following accelerated stress tests:
Thermal shock test:
- Temperature range: -55° to 125°C
- Dwell time: 5 minutes
- Transfer time: <2 minutes
- Target cycle: 250 cycles
Temperature cycling test:
- Temperature range: 0° to 100°C
- Dwell time: 5 minutes
- Transfer time: 10 minutes
- Target cycle: 2,000 cycles
- Temperature: 85°C
- Humidity: 85 percent RH
- Target time: 336 hours
High temperature storage test:
- Temperature: 125°C
- Target time: 336 hours
Testing of the first assembled qualification vehicles completed the target cycles or times. However, to ensure accuracy, testing continued through additional cycles. The summary of the reliability test results on the first test vehicle is shown in Table 4.
DiscussionThe results of the thermal shock, temperature cycling, temperature/humidity and high-temperature storage tests met specifications, with the exception of temperature-cycle failures of the CSP type C, a ceramic rigid-base CSP.
The CSP type C temperature-cycle failures (electrical discontinuities) were detected in certain daisy chains and joints located at corner sections of the component. This might be explained by the fact that the corner joints had been stressed the most because of CTE mismatch between ceramic rigid bases, roughly 5 ppm/°C, and PCB (FR-4), about 16 ppm/°C.
Figure 4. Cumulative number of failed daisy chains in temperature cycling test by location on the CSP.
Figure 4 shows cumulative numbers of failed daisy chains sorted by areas of daisy chains on the CSP. Joint failures first began from the four corners and then spread toward the center of the component with the additional temperature cycles. Similar joint failure patterns of the CSP type C were also observed during thermal-shock tests. Even though the target of 250 thermal-shock cycles had been achieved with no failure, continued tests revealed that the joint failure patterns were similar to those observed during the temperature-cycle test on the CSP type C.
To improve the reliability of the joints, the manufacturer of the CSP type C refined their design with larger joint pads at all four corners. This refinement would make the ceramic CSP joints more reliable. The second test vehicle had three different ceramic CSPs from two different manufacturers, which were CSP type C 308 and type F with different I/O numbers, 224 and 248. Those ceramics-based rigid interposer types of CSPs were already modified in pad designs with the enlarged corner pads. The enlarged pads on the type C 308 were 1.3 mm in diameter instead of the original 0.5 mm pad size. On the type F, the enlarged sizes were 1.5 and 0.8 mm diameters instead of 0.5 mm for the 224 I/O CSP and 0.3 mm for the 248 CSP, respectively. Such enlarged corner pads were expected to reinforce solder joints at the corners to help the CSPs achieve improved results on the reliability tests.
In the first study, CSP type C 324 test vehicles were grouped into four assembly conditions. Group A had double-sided assembly and an optimum joint height placement of 0.005". Group B had single-sided assembly and optimum height. Group C had single-sided assembly and a 0.006" height placement. Group D had double-sided assembly and no adjusted height (about 0.001" lower than the optimum).
Figure 5. Board stiffness dependence on temperature cycle life: CSP type C 324.
For the double-sided assembly, a LQFP 144 I/O was assembled on the opposite side of a CSP type C, so the board stiffness was obviously higher than that of the single-sided assembly (Figure 1). Figures 5 and 6 compare the temperature-cycling test results from the four groups. In the temperature-cycle test, it was determined that the double-sided assembly, with higher board stiffness, had a 1.2X longer lifetime than the single-sided assembly. Since solder volume was controlled, solder joint shapes were dependent on the control of the placement height. This joint shape affected the temperature-cycle test results shown in the plot.
Figure 6. Placement height dependence on temperature cycle life: CSP type C 324.
SummaryFor the implementation and qualification of CSP on-board assembly, two test vehicles were designed in-house on the PC card format. The process implementation was achieved with seven CSPs of four types on the first test vehicle. The second vehicle consisted of eighteen CSPs of fourteen types. This implementation process consisted of five phases: process characterization, preliminary production evaluation, process test run, the production-process confirmation run and qualification. To ensure reliable CSP attachments, solder paste heights and volumes had to be controlled. Therefore, stencil designs, solder print and placement height control were the most critical processes. In the first study, the solder printing process control capabilities over 1.5 of Cpk index were demonstrated. To evaluate the CSP assembly processes, reliability tests on more than 1,000 CSP components and more than 100,000 solder joints were performed and analyzed. These reliability tests included thermal shock, temperature cycling, high-temperature storage and humidity/ temperature testing.
- The paste used for the first study was Alpha Metals LR747. For the second study, the paste used was the UP78.
** The paste was applied using a Quad 100MV printer. A DEK 265LT printer was used on the production line.
ACKNOWLEDGEMENTSThe authors would like to acknowledge the support of their colleagues, including the PCB designers, prototype engineers and manufacturing engineers at the Flextronics International San Jose Product Introduction Center. In particular we would like to thank Lucy Pan, Mark Evans and Guill Muyot.
REFERENCES1 Ron Iscoff, "The Year of the Chip-scale Package?" Chip Scale Review, January/February 1999.
2 K. Nakajima, "CSP Primer for Original Equipment Manufacturers," Chip Scale Review, September 1998.
3 N. Brathwaite, K. Huey and P. Chang, "BGA Assembly Process Qualification and Transfer to Production," Surface Mount International 1997.
4 K. Huey, F. Dong and K. Nakajima, "CSP on Board Assembly Process Qualification," CHIPCON 1998.
5 D. Revelino, "Achieving Single Digit DPMO in SMT Processes," Surface Mount International 1997.
KAZU NAKAJIMA, ALINGTON LEWIS, SAMMY YI and NICHOLAS BRATHWAITE may be contacted at Flextronics International Ltd., 2090 Fortune Dr., San Jose, CA 95131; (408) 576-7000; Fax: (408) 576-7454; Internet: www.flextronics.com.