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Evaluation of Molded Flip-chip BGA Package for 28nm FPGA Applications
September 10, 2013 |Estimated reading time: 1 minute
Abstract
As FPGA device technology migrates to 28nm technology node and high-performance applications, selecting the right package to meet customer usability requirements and to achieve product reliability goals becomes important. This paper describes the process used in selecting and qualifying the molded flip-chip BGA for cost effective, high-performance 28nm FPGA devices. A collaborative approach in partnership with the assembly manufacturer was employed to develop customer collateral that includes handling, reflow/rework, and heatsink attach guidelines for the molded flip-chip BGA package. A detailed thermal modeling of the package was performed to characterize the thermal performance of the package. In addition, compressive loading characterization, component level, and board level reliability tests were carried out to validate the long term reliability performance of the package in customer use conditions. The results of this study demonstrate that the molded flip-chip BGA package is a cost-effective, high-reliability solution for 28nm FPGA devices.
Introduction
Altera has introduced Arria®-V FPGA product family at 28nm technology node to deliver optimized balance of performance, cost and low power for mid-range applications. To meet the device performance and cost goals, selection of packaging technology has become important. The package selected must meet the customer usability requirements and achieve product reliability goals. This paper describes the process used in selecting and qualifying the molded flip-chip BGA package for cost effective, high performance 28nm FPGA devices. To match the low-power, high-performance and low-cost requirements of the 28nm Arria-V FPGAs, a new package platform offered by Amkor Technology, molded flip-chip BGA (Amkor acronym: FCmBGA, Altera acronym: TCFCBGA, Thermal Composite Flip-Chip BGA) was selected. Having an exposed die configuration, FCmBGA inherently offers a low profile form factor. Further the exposed die allows customers flexibility with respect to thermal dissipation solutions. Finally, the replacement of capillary underfill (CUF) with molded underfill (MUF) allows coverage of the 28nm FPGA family with a single package configuration.
In subsequent sections we will describe the methodology for package selection as well as various tests run to provide application guidelines for customers using this package platform. Results for handling during shipping, SMT attach and rework results will be discussed. Heatsink attach/ rework and thermal modeling will also be reviewed. Compressive loading and well as component and board level reliability results will be summarized. Read the full article here.Editor's Note: This article first appeared in the August 2013 issue of SMT Magazine.